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Languguage OS 2
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Languguage OS II Version 10-94 (Knowledge Media)(1994).ISO
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hc05iic.arc
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IIC.S
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1990-06-15
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107 lines
opt mul,cmos,lle=132
* Software for 68hc05 to control IIC peripherals using the SPI interface
* adapted from Naji Naufel's article in EDN, Feb 18 1988
* Port C Bits 0 and 1 are used to generate the start and stop bits required
opt nol
include c4c8reg.s
opt l
asct
data equ PC0 IIC data line controlled by PC0
.data equ .PC0
clk equ PC1 IIC clock line controlled by PC1
.clk equ .PC1
iicport equ PORTC
iicddr equ DDRC
waddr equ 0 IIC write address
raddr equ 1 IIC read address
* init initializes the I/O port hardware
org $50 RAM location - ACK flag
ack rmb 1 set bit 0 to value of ACK bit desired after byte
control rmb 1 RAM location to store control word to IIC device
ram rmb 4 ram buffer for read command
org $100 start of ROM
init lda #.data+.clk set clock and data high
sta iicport
sta iicddr both bits output
clr SPCR make sure SPI is didsabled to start
rts done
* w_start transfers a byte from the HC05 SPI to the IIC peripheral
* Including a start bit. nostart sends the byte with no start bit
* On entry the data is in the accumulator
w_start bclr data,iicport set data line low - start bit
bclr clk,iicport drive clock low
nostart ldx #.SPE+.MSTR enable spi
stx SPCR
bset data,iicport let data line go high
sta SPDR send the data
wait brclr SPIF,SPSR,wait poll while data shifted out
* set SPIE bit for interrupt-driven transfer
lda SPCR disable SPI
and #.SPE!X$ff
sta SPCR
brset 0,ack,hiack test value of ack bit desired
bclr data,iicport ack must be low - clear data line
bsr hiack generate clock pulse
bset data,iicport let data go high again
rts
hiack bset clk,iicport pulse clock high, then low
brn hiack delay - 3 'E' clocks
bclr clk,iicport
rts
* This subroutine creates a stop condition
stop bclr data,iicport strobe data low
bset clk,iicport positive edge on clock line
bset data,iicport put data back to idle state
rts
* This subroutine sends an address byte, followed by a control byte in CONTROL
addrcnt lda #waddr load address value
bsr w_start send with start bit
lda control get desired control value
bsr nostart send without start bit
rts done
* This subroutine reads four bytes from the peripheral
read clr control control = 0
bset 0,ack ack bit should be 1
bsr addrcnt send address followed by control
bsr stop send stop bit
lda #raddr now send read address
bsr w_start
bclr 0,ack ack bit is 1
lda #$ff read 4 bytes - must send ones during process
bsr nostart
lda SPDR get received data
sta ram+2 save in RAM
lda #$ff read 4 bytes - must send ones during process
bsr nostart
lda SPDR get received data
sta ram+3 save in RAM
lda #$ff read 4 bytes - must send ones during process
bsr nostart
lda SPDR get received data
sta ram+1 save in RAM
bset 0,ack last byte has ack bit set to 1
lda #$ff read 4 bytes - must send ones during process
bsr nostart
bsr stop send stop bit
lda SPDR get received data
sta ram save in RAM
rts done
end